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VSC6134ST-01 参数 Datasheet PDF下载

VSC6134ST-01图片预览
型号: VSC6134ST-01
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC,]
分类和应用:
文件页数/大小: 438 页 / 4019 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VSC6134  
Datasheet  
1.1.2  
Line-Side EFEC/OTU Interface Features  
Generation and termination features of the digital wrapper (OTU frames overheads according to ITU-T  
G.709 or Vitesse proprietary EFEC frames and T1X1 digital wrapper) include the following:  
Frame alignment with provisionable frame alignment signal (FAS).  
Provisionable out of frame (OOF) and loss of frame (LOF) detection.  
Optional scrambling and descrambling compliant with ITU G.709.  
Insertion and extraction of the OTU digital wrapper overhead through serial I/O using an external  
FPGA.  
On-chip generation and termination of the OTU digital wrapper overhead bytes MFAS (multiframe  
indication), BIP-8 (bit interleaved parity), TTI (trail trace identifier), and BI (backward indication).  
On-chip generation and detection of OTU-AIS, ODU-AIS, OCI, and LCK.  
On-chip termination of BIP-8 including detection and accumulation of single-bit and block errors.  
Synchronous and asynchronous payload mapping and demapping.  
FEC decoder (Rx) to FEC encoder (Tx) loopback.  
Bit error and framed PRBS insertion and detection for test and verification.  
Optional correction of the FEC signal regeneration of the tandem connection monitoring (TCM)  
fields (BIP-8, TTI, BDI, BEI, STAT). Six TCM fields can be processed simultaneously.  
1.1.3  
Forward Error Correction (FEC) Features  
The forward error correction features are:  
Standard FEC (RS) or EFEC modes (BCH-BCH concatenated), both with 7.1% overhead  
16x interleaving and de-interleaving according to ITU-T G.709  
(255, 239) Reed Solomon encoding (RS mode)  
(3904, 3832) BCH encoding (outer concatenated EFEC code)  
(1904, 1640) BCH encoding (inner concatenated EFEC code)  
Iterative decoding in EFEC mode (BCH-BCH)  
Optional EFEC or OTU frame scrambling and descrambling  
Error counters for total number of correctable errors, total number of uncorrectable blocks (that is,  
255-byte RS codeword)  
Error counters for total number of 0 errors; 1 errors; and in Standard FEC mode, 3-bit pattern  
matching errors  
Provisonable standard FEC disable for interworking of equipment supporting FEC with equipment  
not supporting FEC  
Optional disable of error correction (error monitoring mode only)  
1.1.4  
Client-Side OTU Interface Features  
The client-side OTU interface features are:  
Frame alignment with provisionable frame alignment signal (FAS).  
Provisionable out of frame (OOF) and loss of frame (LOF) detection.  
Optional scrambling and descrambling compliant with ITU G.709.  
Insertion and extraction of the OTU digital wrapper overhead through serial I/O, using an external  
FPGA.  
36 of 438  
VMDS-10185 Revision 4.0  
July 2006