VSC6134
Datasheet
1
Product Overview
The VSC6134 is a bidirectional transport processor, providing forward error correction (FEC),
SONET/SDH section and line processing, 10 Gbps Ethernet (GbE) performance monitoring, and
G.709 digital-wrapper processing for fiber optic transmission lines operating at approximately 10 Gbps.
The VSC6134 has West and East ports. The West port is capable of generating and terminating a
digital-wrapper-compliant OTU2 with standard FEC or Vitesse EFEC interface. The East port can
optionally generate/terminate a SONET/SDH OC-192 interface, a digital-wrapper-compliant OTU2
interface with optional standard FEC, or a transparent interface, configurable using a generic
microprocessor interface. The transparent interface can accept 10.3125 Gbps 64b/66b coded data with
monitoring of 10 GbE statistics in both add and drop paths. Optional RS(255,239) coders are available
on both the West and East side ports and support digital wrapper compliant add/drop, FEC regeneration
and FEC to EFEC domain bridging applications. Synchronous or asynchronous mapping of
SONET/CBR10G payload is also supported.
Both ports support 16-bit SFI-4 compliant (OIF1999.102.8) LVDS synchronous interfaces. Full
bidirectional access to the G.709 digital wrapper overhead is provided on East and West ports using
on-chip generation/termination or external FPGA control. SONET/SDH section and line overhead can
be accessed using the microprocessor register or serial FPGA interface.
1.1
Device Features
The key features of VSC6134 are summarized in the following sections.
1.1.1
SONET/SDH Interface Features
The SONET/SDH interface features for the VSC6134 include the following section and line processing,
which meet the ITU-T G.707, ITU-T G.783, Telcordia GR-253, and ANSI T1.105 standards:
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Frame alignment to SONET/SDH standard framing pattern with provisionable framing pattern
Provisionable severely errored frame (SEF) and loss of frame (LOF) detection
Optional scrambling and descrambling
Detection and accumulation of B1 BIP-8 single-bit and block errors
Bit error ratio (BER) processing; signal degrade (SD) and signal fail (SF) with provisionable
thresholds
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J0/Z0, E1/F1, D1-D3 processing
E2, D4-D12, K1, K2, S1, and M1/M0 processing
Automatic AIS-L generation on LOS and LOF
Framing and BIP-8 test error insertion
Protection switching loopback
Bypass mode for transparent interface of non-SONET/SDH payload
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
