VSC6134
Datasheet
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The access type to RO was corrected and the statement in the bit description for bits 15:0 stating
that the registers were for test or simulation purposes only was removed from the following
registers:
DW Overhead Monitor FTFL FIFO Access
DW Tandem Connection Monitor TTI FIFO Access
DW Path Monitor TTI FIFO Access
DW PSI FIFO Access
Framed PRBS Error Count Register (MSB)
Framed PRBS Error Count Register (LSB)
For more information, see “Registers,” page 201.
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In the DW Section Monitor TTI FIFO register, the bit description for bits 15:0 was replaced and the
access type was corrected. For more information, see Table 241, page 304.
In the Drop PRBS Generator Configuration register, the bit settings in the bit description was
corrected for bit 12 so that 1 is no invert and 0 is invert. For more information, see Table 389,
page 360.
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In the Global MPU Register 2 – One-Second Pulse Software Control, the bit name referenced in the
description for bit 15 was changed from SECP_CLK_SEL[3:0] to SECP_SOURCE_SEL. For
more information, see Table 400, page 366.
In the Global MPU Register 7– Global Sync Status Mask, the second sentence in the bit
descriptions for bit 15 and bit 13 were corrected to state stuff bytes not stop bytes. For more
information, see Table 405, page 369.
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In the Global MPU Register 12 – Interface Control, bit 15 was changed to a reserved bit with read
only access. For more information, see Table 410, page 372.
A design considerations section was added that lists the items that deviate from established
standards. For more information, see “Design Considerations,” page 433.
The BER default configuration table was removed, because it was redundant. For more information
about BER, see “Bit Error Rate (BER) Monitor,” page 57.
The bit names used for the framed PRBS monitor were renamed to remove the OTUK_ prefix. For
more information, see “Framed PRBS Monitor,” page 136.
MPUCLK was removed from the table for input clocks and typical frequencies. The title and
column heading were clarified to indicate typical frequency. For more information, see Table 71,
page 192.
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Information about the Intel Asynchronous mode—Read Cycle and Write Cycle was restored. It was
omitted in revision 2.5 of this datasheet. For more information, see “Intel Asynchronous Mode—
Read Cycle,” page 403 and “Intel Asynchronous Mode—Write Cycle,” page 404
Revision 2.5
Revision 2.5 of this datasheet was published on November 22, 2005. This was the first publication of the
document by Vitesse. The changes for this release included:
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The line DCC bytes from D4 to D12 are shifted by one byte.
New registers were added at the following addresses:
0x4A1
0x742
0x743
0x744
0x745
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
