VSC6134
Datasheet
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Additional bit setting information was provided in the bit descriptions for the following registers:
0x330
0x700
0xF00
0xF02 and 0x702
0xF04 and 0x704
0xF06 and 0x706
0xF08 and 0x708
0xF0A and 0x70A
0xF0C and 0x70C
For more information, see “Registers,” page 201.
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The bit descriptions for the Add/Drop TTI Generator FIFO Pointer register were modified to
include the Drop Path addresses for the Add/DropGenerator SM TTI FIFO Access and
Add/DropGenerator PM TTI FIFO Access register. For more information, see “Add/Drop TTI
Generator FIFO Pointer Register,” page 265.
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The Pulse Width Modulation Control 0 register and Pulse Width Modulation Control 1 register
were removed, and the VCO Mode Control register was added. For more information about VCO
Mode Control, see “VCO Mode Control Register,” page 279.
The RLL Justification Reversal Direction register was modified to show one row for bits 15:6 with
a reset value of 0xFC. For more information, see “RLL Justification Reversal Direction Register,”
page 279.
Information about using the MPU access to clear bits 15:8 was removed from the following
registers:
DW Overhead Monitor Status Register 0
DW Overhead Monitor Status Register 1
DW Section Monitor Status Register
DW Tandem Connection Monitor Status Register
DW Path Monitor Status Register [bits 15:10, and 8}
For more information, see “Registers,” page 201.
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The access type to RO for bits 15:0 was corrected for the registers with the following addresses:
0xF10 – 0xF1D
0x710 – 0x71D
0xF2A – 0xF2F
0x72A – 0x72F
0xF32 – 0xF37
0x732 – 0x737
0xF3A – 0xF63
0x73A – 0x767
For more information, see “Registers,” page 201.
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In the DW PSI Monitor Configuration register, the add and drop register address information was
added for the PSI live bits to the description for bit 7. For more information, see Table 291,
page 320.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
