VSC6134
Datasheet
edge (T
). The minimum values for the hold time after rising clock edge (T
) and hold time
HFSI
HFSI
after rising clock edge (T ) were modified from 1 ns to 3 ns. For more information, see
HDI
Table 438, page 394.
●
The table title was changed from Receive Interface (SONET/SDH Input Mode) to Receive
Interface. A footnote was added to the clock period and clock pulse variation parameters noting
variations in FEC mode due to internal clock gapping. The maximum values for the arrival before
rising clock edge (T
) and the arrival before rising clock edge (T
) parameters were
DDO
DFSO
removed. For more information, see Table 439, page 395.
●
●
In the SONET/SDH Serial Interface – Receive Interface (Overhead Extract) section, the Receive
Interface (FEC Input Mode) table and the Receive Interface (Legacy FEC Input Mode) table were
merged into the Receive Interface table. For more information, see Table 439, page 395.
The table title was changed from Transmit Interface (SONET/SDH Input Mode) to Transmit
Interface. The maximum value for the arrival before rising clock edge parameter was removed. The
minimum value for the setup to rising clock edge parameter was changed from 65 ns to 75 ns. The
T
parameter was changed from “Hold time” to “Hold to rising clock edge.” For more
DDO
information, see Table 440, page 396.
●
●
In the SONET/SDH Serial Interface – Transmit Interface (Overhead Insert) section, the Transmit
Interface (FEC Input Mode) table and the Transmit Interface (Legacy FEC Input Mode) table were
merged into the Transmit Interface table. For more information, see Table 440, page 396.
In the Operating Conditions section, a new row for LVTTL I/O supply current was added to the
Recommended Operating Conditions table. The minimum value for the core supply current
parameter and the minimum value for the I/O supply current parameter were removed. The
maximum value for the I/O supply current parameter was changed from 1.06 A to 1.1 A. For more
information, see Table 450, page 405.
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●
●
●
In the Stress Ratings section, the core supply current parameter and the I/O supply current
parameter were removed.
In the Power Supply Dissipation Requirements section, the 1.2 V Core Supply Power
Dissipation - EFEC Mode table was removed.
In the Power Supply Dissipation Requirements section, the 1.2 V Core Supply Power Dissipation
table was replaced. For more information, see Table 453, page 406.
In the Power Supply Dissipation Requirements section, the maximum for the power dissipation was
changed from 2.8 W to 2.9 W and the minimum value in the 2.5 V Core Supply Absolute
Maximum Power Dissipation table was removed. For more information, see Table 454, page 406.
●
In the Power Supply Dissipation Requirements section, a 1.2 V Core Supply Absolute Maximum
Power Dissipation table, a 3.3 V LVTTL Supply Power Dissipation table, and a Total Power table
was added. For more information, see Table 452, page 406, Table 455, page 406, and Table 456,
page 406.
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●
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In the Microprocessor Interface Pins section, the description for the MPU_CLK pin (T3) was
changed from when MPU_CLK is 0 to the clock should be 50 MHz. For more information, see
Table 458, page 407.
In the JTAG Interface Pins section, information in the description for the JTAG test mode select pin
(AH32) was added about tying it high to V
information, see Table 467, page 418.
(2.5 V) to ensure functional operation. For more
DDIO
The bit description for DROP_TST_PRBS in the Drop Encoder General Configuration Register 1
was modified to match the bit description for the ADD_TST_PRBS in the Add Encoder General
Configuration Register 1. For more information, see Table 155, page 256.
29 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
