VSC6134
Datasheet
Revision History
This section describes the changes that were implemented in this document. The changes are listed by
revision, starting with the most current publication.
Revision 4.0
Revision 4.0 of this datasheet was published in July 2006. This section contains a summary of the
changes implemented in the datasheet. For more information about the changes, contact your Vitesse
Applications Engineer. The changes are as follows:
●
The electrostatic discharge voltage limits for charged device model and human body model were
added. For more information, see “Stress Ratings,” page 405.
●
The VSC6134-01 is now available. This part is designed for use in 2.5 Gbps applications. The part
is available in two packages: VSC6134ST-01 and VSC6134XST-01, a lead(Pb)-free package. For
more information, see Table 471, page 431 and Table 472, page 437.
●
●
Thermal specifications were added for the device. For more information, see “Thermal
Specifications,” page 431.
The MSL rating was changed to MSL 4. For more information, see “Moisture Sensitivity,”
page 431.
●
●
The asynchronous mode for Motorola was removed.
The chip select fast (early) setting was removed from the synchronous modes for Intel and
Motorola. The chip select slow (late) is the setting used for these modes.
●
●
In the Microprocessor Interface Characteristics section, the General Microprocessor Interface
Characteristics table was updated. For more information, see Table 441, page 396.
In the Motorola Pseudo-Synchronous Mode – Read Cycle section, the row for the Hold time for csn
assert/de-asserted to mpu_clk rise parameter was removed, and the maximum value for the delay
from asn de-asserted to dtkn de-asserted parameter was changed from 8 ns to 10 ns. For more
information, see Table 442, page 397.
●
In the Motorola Pseudo-Synchronous Mode – Write Cycle section, the row for the Hold time for
csn assert/de-asserted to mpu_clk rise parameter was removed, and the maximum value for the
delay from asn de-asserted to dtkn de-asserted parameter was changed from 8 ns to 10 ns. For more
information, see Table 443, page 398.
●
●
In the Motorola Synchronous Mode – Read Cycle section, “Slow CSN” was removed from the
section name, table title, figure title, parameters, and text.
In the Motorola Synchronous Mode – Read Cycle section, the row for the Hold time for csn
assert/de-asserted to mpu_clk rise parameter was removed. The delay for mpu_clk rise to tan
de-asserted parameter was changed from 8 ns to 16 ns, and the delay for mpu_clk rise to tan
asserted parameter was changed from 8 ns to 16 ns. For more information, see Table 444, page 399.
●
In the Motorola Synchronous Mode – Write Cycle section, the row for the Hold time for csn
assert/de-asserted to mpu_clk rise parameter was removed. The delay for mpu_clk rise to tan
de-asserted parameter was changed from 8 ns to 16 ns, and the delay for mpu_clk rise to tan
asserted parameter was changed from 8 ns to 16 ns. For more information, see Table 445, page 400.
●
In the Intel Synchronous Mode – Read Cycle section, “Slow CSN” was removed from the section
name, table title, figure title, parameters, and text.
27 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
