VSC6134
Datasheet
Table 402 Global MPU Register 4 - One-Second Pulse LSW Count....................................................367
Table 403 Global MPU Register 5 - One-Second Pulse Clock and Source Control.............................367
Table 404 Global MPU Register 6 - Global Configuration Control 1.....................................................368
Table 405 Global MPU Register 7 - Global Sync Status Mask.............................................................369
Table 406 Global MPU Register 8 - Global Sync Status.......................................................................370
Table 407 Global MPU Register 9 - Device ID......................................................................................371
Table 408 Global MPU Register 10 - Device Version...........................................................................371
Table 409 Global MPU Register 11 - Scratch.......................................................................................372
Table 410 Global MPU Register 12 - Interface Control.........................................................................372
Table 411 Global MPU Register 13 - Block Interrupts ..........................................................................373
Table 412 Global MPU Register 14 - Loss of Clock Mask....................................................................374
Table 413 Global MPU Register 15 - Loss of Clock Interrupt Status....................................................375
Table 414 Global MPU Register 16 - Global Configuration Control 2...................................................376
Table 415 Global MPU Register 17 - FEC Mode Register....................................................................377
Table 416 Global MPU Register 18 - Power-Down Register ................................................................378
Table 417 Global MPU Register 19 - Correction Register ....................................................................379
Table 418 Global MPU Register 20 - SerDes Control Register ............................................................379
Table 419 Global MPU Register 25 - Add SONET Enables .................................................................381
Table 420 Global MPU Register 26 - Drop SONET Enables................................................................382
Table 421 Global MPU Register 27 - Phase/Frequency Discriminator Register...................................383
Table 422 Global MPU Register 28 - Add PFD RX Clock Ratio Register.............................................384
Table 423 Global MPU Register 29 - Add PFD TX Clock Ratio Register .............................................384
Table 424 Global MPU Register 30 - Drop PFD RX Clock Ratio Register ...........................................384
Table 425 Global MPU Register 31 - Drop PFD TX Clock Ratio Register............................................385
Table 426 Global MPU Register 32 - SONET Block Interrupts.............................................................385
Table 427 Global MPU Register 33 - Global Client Interface Configuration Register 0........................386
Table 428 Global MPU Register 34 - Global Client Interface Configuration Register 1........................386
Table 429 Global MPU Register 35 - Block Interrupt Mask ..................................................................387
Table 430 LVTTL Characteristics..........................................................................................................389
Table 431 3.3 V LVTTL Driver Slew Rate.............................................................................................389
Table 432 LVDS Receiver DC Characteristics......................................................................................390
Table 433 LVDS Driver DC Characteristics ..........................................................................................390
Table 434 LVDS Receive......................................................................................................................391
Table 435 LVDS Transmit.....................................................................................................................392
Table 436 Phase Frequency Discriminator Characteristics ..................................................................392
Table 437 Receive Interface .................................................................................................................393
Table 438 Transmit Interface ................................................................................................................394
Table 439 Receive Interface .................................................................................................................395
Table 440 Transmit Interface ................................................................................................................396
Table 441 General Microprocessor Interface Characteristics...............................................................396
Table 442 Motorola Pseudo-Synchronous Mode—Read Cycle............................................................397
Table 443 Motorola Pseudo-Synchronous Mode—Write Cycle............................................................398
Table 444 Motorola Synchronous Mode—Read Cycle.........................................................................399
Table 445 Motorola Synchronous Mode—Write Cycle .........................................................................400
Table 446 Intel Synchronous Mode—Read Cycle ................................................................................401
Table 447 Intel Synchronous Mode—Write Cycle ................................................................................402
Table 448 Intel Asynchronous Mode – Read Cycle..............................................................................403
Table 449 Intel Asynchronous Mode – Write Cycle ..............................................................................404
Table 450 Recommended Operating Conditions..................................................................................405
Table 451 Absolute Maximum Ratings .................................................................................................405
Table 452 1.2 V Core Supply Absolute Maximum Power Dissipation...................................................406
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
