VSC6134
Datasheet
Five asynchronous clocks are provided to the VSC6134. The four high-speed clocks are divided by four
to generate the clocks for the four major asynchronous data domains (rxclk_client, txclk_client,
rxclk_line, txclk_line).
The following table indicates the input clocks and their typical frequencies.
Table 71. Input Clocks and Typical Frequencies
Typical
Frequency
Clock
Description
Mode
RXCLK1, TXCLKSRC1
Receive client side clock,
Transmit client side clock
622.08 MHz
666.51 MHz
669.33 MHz
644.53 MHz
690.57 MHz
SONET/SDH
FEC without stuff columns
FEC with stuff columns
10 GbE
10 GbE with FEC without stuff
columns
693.48 MHz
10 GbE with FEC with stuff
columns
624.69 MHz
622.08 MHz
666.51 MHz
669.33 MHz
690.57 MHz
OPU2 payload
RXCLK0, TXCLKSRC0
Receive line side clock,
Transmit line side clock
SONET/SDH
FEC without stuff columns
FEC with stuff columns
10 GbE with FEC without stuff
columns
693.48 MHz
10 GbE with FEC with stuff
columns
Four asynchronous on-chip system clock domains are defined, from which all other subdomains are
derived by gating (for block power-down) and gapping (for data rate change). A functional diagram of
the clock generation is shown in Figure 72.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
