VSC6134
Datasheet
The following figure shows the timing diagram for the read operation.
Figure 68. Timing for a Read Operation of Asynchronous Intel Microprocessors
register_address
addr[11:0]
ale
S0
H 0
S5
H 2
S2
S3
csn
rdn
H3
D0
D5
D2
D4
D6
D1
rdy
D3
data[15:0]
mpu_clk
Data
Notes:
●
●
The address is latched into a level-sensitive latch on the falling edge of ALE.
A bus cycle is recognized when the synchronized CSN NOR RDN is high. CSN and RDN must be
clocked to the same rising edge of MPU_CLK.
●
●
●
MPU_CLK is 50 MHz and is synchronous to the microprocessor clock.
RDY is de-asserted on the rising edge of RDN.
RDY is tristated when the synchronized CSN NOR RDN signal is detected unless DTK_TRI_PRG
is set to 1.
●
DATA[15:0] is tristated on the rising edge of RDN and on the rising edge of CSN.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
