VSC6134
Datasheet
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RDYRCVN is asserted only for one clock cycle.
DATA[15:0] is tristated on the rising edge of the clock when RDYRCVN is de-asserted.
Write Operation
The following figure shows a flowchart of the sequence of events for a write operation.
Figure 65. Write Operation Sequence for Intel Synchronous Interface
Microprocessor
VSC6134
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Place Address on
ADDR[11:0]
Set WRN =1
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Latch Address
Determine Read or
Write Command
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Strobe ADSN.
Place Data on DATA[15:0]
Tristate DATA[15:0]
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Latch Data
Write Data to Register
Assert RDYRCV
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Negate RDYRCV
Start New Cycle
185 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
