VSC6134
Datasheet
Read Operation
The following figure shows a flowchart of the sequence of events for a read operation:
Figure 63. Read Operation Sequence for Intel Synchronous Interface
Microprocessor
VSC6134
•
Place Address on
ADDR[11:0]
Set WRN =’0’
Strobe ADSN.
•
•
Latch Address
Determine Read or
Write Command
Read Register
Drive DATA [15:0] with
Read Data
•
•
•
•
•
Assert RDYRCVN
Latch Data
Start New Cycle
•
•
Tristate DATA[15:0]
Negate RDYRCVN
The following figure shows the timing diagram for the read operation.
Figure 64. Timing for a Read Operation of Synchronous Intel Microprocessors
mpu_clk
addr[11:0]
register_address
S0
adsn
D0
S1
csn
wrn
S2
D3
D2
D1
D4
rdyrcvn
D5
data[15:0]
Data
Notes:
●
Address is latched on the rising of the clock when ADSN is asserted. This also indicates the start of
a bus cycle.
184 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
