VSC6134
Datasheet
Figure 55. Read Operation Sequence for Motorola Pseudo-Synchronous Interface
Microprocessor
VSC6134
•
Place Address on
ADDR[11:0]
Assert ASN.
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Latch Address
Determine Read or
Write Command
Read Register
Drive DATA [15:0] with
Read Data
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Set RWN =1
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Assert DTKN
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Detect DTKN
Latch Data
Negate ASN
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Tristate DATA[15:0]
Negate DTKN
Start New Cycle
Note that the microprocessor detects the DTACKN signal on the falling edge of the internal clock and
then waits until the next falling edge before latching data.
176 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
