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VSC6134ST-01 参数 Datasheet PDF下载

VSC6134ST-01图片预览
型号: VSC6134ST-01
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC,]
分类和应用:
文件页数/大小: 438 页 / 4019 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VSC6134  
Datasheet  
2.16  
Microprocessor Interface Description  
This section describes the microprocessor interface unit (MPIU) of the VSC6134. This unit has four  
primary functions:  
Write register— Receives data and addresses from an external microprocessor and writes the data  
into the register indicated by the address.  
Read register—Receives an address from the microprocessor, reads the contents of the address and  
transmits them back to the microprocessor.  
Delivers acknowledgement of writes/reads to the microprocessor.  
Delivers interrupts to the microprocessor.  
When reading the 32-bit counter cache registers, the microprocessor must read the 16-bit MSB of the  
count first (bits 31:16), at which time the 16-bit LSB of the count (bits 15:0) is transferred to a shadow  
register. When the microprocessor reads the 16-bit LSB of the count, it is the shadow register that is  
read.  
2.16.1  
External Microprocessor Modes and Timing  
The microprocessor interface unit (MPIU) of the VSC6134 is capable of interfacing with both Motorola  
and Intel microprocessors. The MPIU uses the MPSEL pin to determine the type of microprocessor  
interface being used (Motorola or Intel). Synchronous or asynchronous operation is determined by the  
MPMODE pin. A third pin, SYNSEL_DSN_WRN, determines the synchronous or pseudo-synchronous  
mode to Motorola processors.  
The following table lists the external signals that connect to the MPIU.  
Table 65. External Microprocessor Interface Signals  
Signal  
Function  
MPU_CLK  
ASN_ALE  
Microprocessor clock  
1. Address strobe  
2. Address latch enable  
CSN  
Chip select  
SYNSEL_DSN_WRN  
1. Select synchronous mode (0 = pseudo-synchronous, 1 = synchronous)  
2. Data strobe  
3. Write strobe  
RWN_WRN_RDN  
1. Read/Write  
2. Write/Read  
3. Read strobe  
MPMODE  
MPSEL  
0 - Asynchronous (Intel only)  
1 - Synchronous  
0 - Motorola  
1 - Intel  
DTKN_RDY  
INTN  
1. Data acknowledge  
2. Ready  
Interrupt  
173 of 438  
VMDS-10185 Revision 4.0  
July 2006  
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