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VSC6134ST-01 参数 Datasheet PDF下载

VSC6134ST-01图片预览
型号: VSC6134ST-01
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC,]
分类和应用:
文件页数/大小: 438 页 / 4019 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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3  
p  
VSC6134  
Datasheet  
2.14  
Programmable PRBS Generator and Checker  
The pseudo-random bit sequence generator and checker (monitor) blocks are used to transmit and  
receive pseudo-random sequences of programmable length through the line interface. The primary  
intention is to generate sequences of zeros of known length to stress the clock and data recovery  
function of the off-chip serializer and deserializer (SerDes) modules. The PRBS generator and monitor  
can also be used for other test purposes. There are two sets of PRBS generators and checkers on both the  
line and client ports. Note that in addition to configuring the PRBS registers, the PRBS_SEL muxes  
must also be configured in the FEC mode registers (ADD_FEC_PRBS_SEL and  
DROP_FEC_PRBS_SEL). The PRBS generators and monitors and their connections are shown in the  
following figure.  
Figure 34. Functional Diagram with PRBS Generators/Monitors  
Add Path  
10 GbE  
MAC  
Stats  
PRBS  
Generator  
PRBS  
Monitor  
64B/66B  
Decoder  
ADD_FEC_PRBS_SEL  
SONET/  
SDH  
Processor  
RS FEC  
Encoder  
DW  
Monitor  
RS FEC  
Decoder  
16  
DW  
Generator  
622.08/669.33/  
690.25 Mbps  
16  
622.08/624.70/  
644.53/669.33/  
690.25 Mbps  
EFEC  
Encoder  
Network (East) Interface  
Line (West) Interface  
SONET/  
SDH  
Processor  
EFEC  
Decoder  
RS FEC  
Encoder  
DW  
Generator  
DW  
Monitor  
RS FEC  
Decoder  
16  
16  
622.08/669.33/  
690.25 Mbps  
622.08/624.70/  
644.53/669.33/  
690.25 Mbps  
10GbE  
MAC  
Stats  
64B/66B  
Decoder  
PRBS  
Monitor  
PRBS  
Generator  
DROP_FEC_PRBS_SEL  
L  
Drop Path  
Clock Dividers and  
Phase-Frequency  
Detectors  
FPGA Serial  
Interface  
Microprocessor  
Interface  
148 of 438  
VMDS-10185 Revision 4.0  
July 2006  
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