622.08/624.
644.53/669.3
690.25 Mbp
VSC6134
Datasheet
2.14
Programmable PRBS Generator and Checker
The pseudo-random bit sequence generator and checker (monitor) blocks are used to transmit and
receive pseudo-random sequences of programmable length through the line interface. The primary
intention is to generate sequences of zeros of known length to stress the clock and data recovery
function of the off-chip serializer and deserializer (SerDes) modules. The PRBS generator and monitor
can also be used for other test purposes. There are two sets of PRBS generators and checkers on both the
line and client ports. Note that in addition to configuring the PRBS registers, the PRBS_SEL muxes
must also be configured in the FEC mode registers (ADD_FEC_PRBS_SEL and
DROP_FEC_PRBS_SEL). The PRBS generators and monitors and their connections are shown in the
following figure.
Figure 34. Functional Diagram with PRBS Generators/Monitors
Add Path
North (Add ) Path
10 GbE
MAC
MAC
Stats
Stats
10GbE
PRBS
PRBS
Generator
Generator
PRBS
PRBS
Monitor
Monitor
64B/66B
64B/66B
Decoder
Decoder
ADD_FEC_PRBS_SEL
ADD_FEC_PRBS_SEL
SONET/
SONET/
SDH
SDH
Processor
Processor
RS FEC
Encoder
Encoder
RS FEC
DW
DW
Monitor
Monitor
RS FEC
RS FEC
Decoder
Decoder
16
16
DW
DW
Generator
Generator
622.08/669.33/
622.08/669.33/
690.25 Mbps
690.25 Mbps
16
16
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644.53/669.33/
690.25 Mbps
690.25 Mbps
622.08/624.70/
EFEC
EFEC
Encoder
Encoder
Network (East) Interface
Network (East) Interface
Line (West) Interface
Line (West) Interface
SONET/
SONET/
SDH
SDH
Processor
Processor
EFEC
EFEC
Decoder
Decoder
RS FEC
RS FEC
Encoder
DW
DW
Generator
DW
Monitor
i
RS FEC
Decoder
16
16
16
16
622.08/669.33/
690.25 Mbps
622.08/624.70/
644.53/669.33/
690.25 Mbps
10GbE
MAC
Stats
64B/66B
Decoder
PRBS
Monitor
PRBS
Generator
DROP_FEC_PRBS_SEL
DROP_FEC_PRBS_SEL
South (Drop) Path
Drop Path
Clock Dividers and
Phase-Frequency
Detectors
FPGA Serial
Interface
Microprocessor
Interface
148 of 438
VMDS-10185 Revision 4.0
July 2006