VSC6134
Datasheet
The serializer I/O description is shown in the following table.
Table 61. Serializer Block I/O Description
Name
hw_reset_n
Direction
IN
Function
Hardware reset—Primary input.
sw_reset_n
txclkin16
IN
IN
Software reset generated by microprocessor interface.
High-speed clock—Primary input.
High-speed clock—to serializer for loopback operation.
rxclkin16
IN
txdin[63:0]
systxclk64
sytxsclk64_reset_n
loopback
IN
Low-speed 64-bit parallel data in synced to system clock—systxclk64.
Low-speed system clock from clock tree.
Reset synchronized to systxclk64.
IN
IN
IN
Loopback mode.
txclkout16
txclk64
OUT
OUT
High-speed clock - primary output.
Low-speed system clock from clock divider (1/4 frequency of
high-speed clock) to system clock-tree.
dout[15:0]
OUT
High-speed data out synced to txclk16—Primary outputs.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
