VSC6134
Datasheet
Figure 35. PRBS Checker Block Diagram
prbschk_sel[1:0]
datai[63:0]
L
Parallel
Equation
Generator
Compare
Data
F
S
R
prbschk_inv
Reload
prbschk_ena
Sync/
Reload
FSM
Match Cntr
pat_match
Sync’d
Two status bits are provided to monitor status, PRBSCHK_SYNCS and PRBSCHK_ERRS, in the
PRBS status register. PRBSCHK_SYNCS status bit is set following the assertion of the
PRBSCHK_ENA bit and detection of an in-sync condition. It remains asserted (even if subsequent
errors are detected) until PRBSCHK_ENA is de-asserted or it is cleared. It is cleared on read or on
write, depending on the microprocessor configuration bit CLR_RD_WRN. The PRBSCHK_ERRS
status bit is asserted if the checker is in an insync condition and has detected a mismatch between the
incoming data and the locally generated sequence. PRBSCHK_ERRS is cleared if PRBSCHK_ENA is
de-asserted or it is cleared by the microprocessor (on read or on write). The status bits generate
interrupts if the corresponding interrupt mask bits are cleared.
A 16-bit counter counts the number of bit errors (that is, mismatches between the incoming and locally
generated sequences), PRBSCHK_ERRCNT[15:0]), that are reported in the PRBS checker error count
register. The counter is cleared if PRBSCHK_ENA is de-asserted or it is cleared by a microprocessor
read (assuming the microprocessor configuration bit SAT_ROLLOVERN is set to 1).
2.14.3
Programmable PRBS Generator and Checker Register Information
For information about the programmable PRBS generator and checker registers, see “Programmable
PRBS Generator and Checker Registers,” page 359.
151 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
