VSC6134
Datasheet
Figure 32. LOF State Machine
NO OOF
OOF
NLOF
LOF= 0
Pre-
Aligned
State
Pre-
Alarm
State
1
m-1
LOF= 0 OOF
LOF= 1
NO OOF
OOF
Pre-
Pre
Aligned
Alarm
State
2
LOF= 0
State
2
OOF
OOF
LOF= 1
OOF
NO OOF
Pre-
Aligned
State
1
Pre-
Alarm
State
n-1
LOF= 1
LOF= 0
OOF
LOF
LOF= 1
Reset
On reset, the aligner goes into LOF state and LOF is declared. LOF is cleared when P consecutive
number of frames, with inactive OOFs, are received (P is provisionable using the configuration bits
LOFCLRCNT[10:0], default is 24).
The frame aligner declares LOF when OOF is active for a consecutive Q number of frames (Q is
provisionable using the configuration bits LOFSETCNT [10:0], default is 24 consecutive frames; that is,
3 ms in SONET mode). If INTEGRATING_TIMER is set, then LOF is declared when OOF is active for
Q nonconsecutive frames, provided that OOF does not remain inactive for P consecutive frames during
the gaps. For example, if an active OOF is received for two frames, then the aligner goes in
PreAlarm_state2. After that if OOF is inactive for one frame period, then the state machine remains at
the same state (PreAlarm_state2). The state machine enters into a PreAlarm_state3 next time when an
active OOF is received. If the state machine is at PreAlarm_state2 and OOF remains inactive for
P × frame period, then it returns to the NLOF state. In the state machine diagram for LOF, LOF = 1 is
declared in LOF, and all Pre_aligned states are 0 in IF and all Pre_alarm states. The
INTEGRATING_TIMER mode can be set on or off by a register bit.
The interrupt status bits FERS, OOFS, LOFS and their associated interrupt mask bits, FERM, OOFM,
and LOFM, are used to indicate the frame aligner status and to generate interrupts. The status bits are
cleared on read or on write depending on the microprocessor configuration bit CLR_RD_WRN (0 for
clear on write, 1 for clear on read).
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
