欢迎访问ic37.com |
会员登录 免费注册
发布采购

VSC6134ST-01 参数 Datasheet PDF下载

VSC6134ST-01图片预览
型号: VSC6134ST-01
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC,]
分类和应用:
文件页数/大小: 438 页 / 4019 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
 浏览型号VSC6134ST-01的Datasheet PDF文件第107页浏览型号VSC6134ST-01的Datasheet PDF文件第108页浏览型号VSC6134ST-01的Datasheet PDF文件第109页浏览型号VSC6134ST-01的Datasheet PDF文件第110页浏览型号VSC6134ST-01的Datasheet PDF文件第112页浏览型号VSC6134ST-01的Datasheet PDF文件第113页浏览型号VSC6134ST-01的Datasheet PDF文件第114页浏览型号VSC6134ST-01的Datasheet PDF文件第115页  
VSC6134  
Datasheet  
Forney Algorithm  
This block computes the correction vector to be applied to the original message. The uncorrected  
symbols are presented by the codeword FIFO.  
Codeword FIFO  
This block stores the codewords presented to the decoder and passes them to the Forney block for  
calculation of the corrected codeword.  
Performance  
This block is designed to decode continuous messages with 255 symbols, including 16 parity symbols.  
It provides high-speed, low-latency decoding of Reed Solomon codes. The decoder meets G.975 and  
G.709 ITU-T recommendations.  
Coincidentally with the output of the code symbols, the correction statistics are also produced. These  
statistics include a marker asserted coincidentally with output symbols that have been corrected, the  
total number of errors corrected, and flag to indicate that the code now being output is correctable.  
Core Pinout  
The RS decoder pinout is listed in the following table. All signals are active high unless stated  
otherwise.  
Table 45. RS Decoder Pins  
Signal  
I/O  
IN  
IN  
IN  
Size  
Description  
Clk  
1
1
1
Decoder clock. Rising edge active.  
Asynchronous reset input. Active high.  
Resn  
Frame_Start_In  
Frame start indicator. Asserted coincident with the first valid Data_in of a  
block.  
Data_In(7:0)  
Data_Valid_In  
Dec_En  
IN  
IN  
8
1
1
1
1
8
Symbol data input. Data on the input is valid on the Clk rising edge when  
Data_Valid_In is asserted.  
Symbol data valid indicator. Asserted coincidentally while the symbol data  
input is valid.  
IN  
When high, corrections are done to data; otherwise, uncorrected data is  
output from this block at all times.  
Data_Valid_Out  
Fstart_Out  
OUT  
OUT  
OUT  
Output symbol data valid flag. Asserted coincidentally with data on  
Data_Out generated on the rising edge of Clk.  
Frame start output flag. Asserted coincident with the first valid output  
symbol of a block.  
Data_Out(7:0)  
Symbol data output. Data is valid on the rising edge of Clk when  
Data_Valid_Out is asserted. Data symbols are held valid for the complete  
period between Data_Valid_Out pulses.  
Uncorr  
OUT  
1
111 of 438  
VMDS-10185 Revision 4.0  
July 2006  
 复制成功!