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DG538ADN 参数 Datasheet PDF下载

DG538ADN图片预览
型号: DG538ADN
PDF下载: 下载PDF文件 查看货源
内容描述: 4- / 8通道宽带视频多路复用器 [4-/8-Channel Wideband Video Multiplexers]
分类和应用: 复用器
文件页数/大小: 16 页 / 143 K
品牌: VISHAY [ VISHAY ]
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DG534A/538A  
Vishay Siliconix  
APPLICATIONS (CONT'D)  
A typical switching threshold versus VL is shown in Figure 15.  
Channel address data can only be entered during WR low,  
when the address latches are transparent and I/O is low.  
Similarly, address readback is only operational when WR and  
I/O are high.  
These devices feature an address readback (Tally) facility,  
whereby the last address written to the device may be output  
to the system. This allows improved status monitoring and  
hand shaking without additional external components.  
The Siliconix CLC410 Video amplifier is recommended as an  
output buffer to reduce insertion loss and to drive coaxial  
cables. For low power video routing applications or for unity  
gain input buffers CLC111/CLC114 are recommended.  
This function is controlled by the I/O pin, which directly  
addresses the tri-state buffers connected to the EN and  
address pins. EN and address pins can be assigned to accept  
data (when I/O = 0; WR = 0; RS = 1), or output data (when I/O =  
1; WR = 1; RS = 1), or to reflect a high impedance and latched  
state (when I/O = 0; WR = 1; RS = 1).  
8
7
6
5
When I/O is high, the address output can sink or source  
current. Note that VL is the logic high output condition. This  
point must be respected if VL is varied for input logic threshold  
shifting.  
V
(V)  
th  
4
3
2
1
0
Further control pins facilitate easy microprocessor interface.  
On chip address, data latches are activated by WR, which  
serves as a strobe type function eliminating the need for  
peripheral latch or memory I/O port devices. Also, for ease of  
interface, a direct reset function (RS) allows all latches to be  
cleared and switches opened. Reset should be used during  
power up, etc., to avoid spurious switch action. See Figure 16.  
0
2
4
6
8
10 12 14 16 18  
(V)  
V
L
FIGURE 15. Switching Threshold Voltage vs. V  
L
DG534A  
S
S
CLC410  
A1  
75 ꢀ  
B2  
D
A
B
A , A  
0
1
A
V
= 2  
EN  
CLC410  
D
RS  
75 ꢀ  
Data Bus  
WR  
Reset  
WR  
Address Bus  
DG534A  
S
S
A1  
CLC410  
CLC410  
75 ꢀ  
B2  
D
A
B
A , A  
0
1
Address  
Decoder  
EN  
I/O  
RS  
D
WR  
75 ꢀ  
Video  
Bus  
Data  
Bus  
FIGURE 16. DG534A in a Video Matrix  
Document Number: 70069  
S-05734Rev. G, 29-Jan-02  
www.vishay.com  
16