DG534A/538A
Vishay Siliconix
TEST CIRCUITS
+5 V
+15 V
+
10
mF
V
L
EN
8/4, 4/2
RS
D
A
V
IN
S
A1
I/O
GND WR
A
0
to
A
2
50
W
V
O
S
A2
– S
Bn
V+
100 nF
V–
+
10
mF
–3 V
100 nF
FIGURE 6.
Bandwidth
8/4 or 4/2 = Logic “0”
D
A
R
IN
S
An
V
OUT
All Channels Off
S
A1
S
An
V
OUT
S
B1
S
Bn
D
B
R
L
S
B1
S
Bn
D
B
R
L
75
W
D
A
S
A1
X
TALK(AH)
+
20 log
10
Note: S
A1
on or any other one channel on.
V
OUT
V
X
TALK(CD)
+
20 log
10
V
OUT
V
FIGURE 7.
All Hostile Crosstalk
FIGURE 8.
Chip Disabled Crosstalk
R
IN
10 W
V
Sn–1
S
n–1
V
Sn
S
n
V
Sn+1
R
IN
10
W
S
n+1
R
L
10 kW
S
B1
S
Bn
V
Channels S
A1
and S
B1
On
4/2 = Logic “1”
S
A1
D
A
R
IN
S
An
R
L
D
B
R
L
Signal
Generator
X
TALK(DIFF)
+
20 log
10
V
OUT
V
V
OUT
X
TALK(AI)
+
20 log
10
V
Sn – 1
V
Sn
or 20 log
10
V
Sn
)
1
V
Sn
FIGURE 9.
Adjacent Input Crosstalk
FIGURE 10.
Differential Crosstalk
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
12
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