DG534A/538A
Vishay Siliconix
PIN DESCRIPTION
Pin Number
DG534ADJ DG538A
Symbol
Description
D
A
2
2
Analog Output/Input
V+
3
3
Positive Supply Voltage
Analog Input/Output
Analog Input/Output
Analog Input/Output
Analog Input/Output
4 x 1 or 2 x 2 Select
8 x 1 or 4 x 2 Select
Reset
S
4
4
A1
A2
A3
A4
S
S
S
6
6
–
8
–
10
4/2
8/4
RS
WR
7
–
11
–
8
9
12
13
Write command that latches A, EN
A , A , A
11, 10, –
16, 15, 14
Binary address inputs that determine which channel(s) is/are connected to the out-
put(s)
0
1
2
EN
I/O
12
13
17
Enable. Input/Output, if EN = 0, all channels are open
Input/Output control. Used to write to or read from the address latches
Logic Supply Voltage, usually +5 V
Analog Input/Output
18
V
L
14
19
S
B4
S
B3
S
B2
S
B1
–
20
–
22
Analog Input/Output
15
24
Analog Input/Output
17
26
Analog Input/Output
V–
18
27
28
Negative Supply Voltage
D
B
19
Analog Output/Input
GND
1, 5, 16
1, 5, 7, 9, 21, 23, 25
Analog and Digital Grounds. All grounds should be connected externally to optimize
dynamic performance
APPLICATIONS
Device Description
The DG534A/DG538A are improved pin-compatible
replacements for the non-A versions. Improvements include:
higher current readback drivers, readback of the EN bit,
latchup protection
The DG534A/538A D/CMOS wideband multiplexers offer
single-ended or differential functions. A 8/4 or 4/2 logic input
pin selects the single-ended or differential mode.
Frequency Response
To meet the high dynamic performance demands of video,
high definition TV, digital data routing (in excess of 100 Mbps),
etc., the DG534A/538A are fabricated with DMOS transistors
configured in ‘T’ arrangements with second level ‘L’
configurations (see Functional Block Diagram).
A single multiplexer on-channel exhibits both resistance
[rDS(on)] and capacitance [CS(on)]. This RC combination
causes a frequency dependent attenuation of the analog
signal. The –3-dB bandwidth of the DG534A/538A is typically
500 MHz (into 50 ꢀ ). This figure of 500 MHz illustrates that the
switch-channel cannot be represented by a simple RC
combination. The on capacitance of the channel is distributed
along the on-resistance, and hence becomes a more complex
multi-stage network of R’s and C’s making up the total rDS(on)
Use of DMOS technology yields devices with very low
capacitance and low rDS(on). This directly relates to improved
high frequency signal handling and higher switching speeds,
while maintaining low insertion loss figures. The ‘T’ and ‘L’
switch configurations further improve dynamic performance
by greatly reducing crosstalk and output node capacitances.
and CS(on)
.
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
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