20-33GHz Medium Power Amplifier
Typical Bias Tuning
The circuit schematic is given below :
Vd1
Vg 2
Vd2,3,4
CHA3092
IN
OU
T
Vg1
Vg 2
Vg 3,4
Vdet
For medium power operation, the four drain biases are connected altogether. In a same way, all the
gate biases are connected together at the same power supply, tuned to drive a small signal operating
current of 300mA. A separate access to the gate voltages of the two first stages ( Vg1,2 ) is provided in
order to be able to tune the first stages for the application, as a lower noise amplifier or a multiplier.
An additional pad is provided for monitoring the output power, using the Build In Test. This access,
when connected to an external resistor of 10 kOhm ( typical value ) provides a DC voltage which
follows the output power level.
Note : In order to minimize the chip to chip performance spread, it is recommended to bias the chip at
fixed drain current Id rather than at fixed Vg voltage.
In addition, to prevent unwanted self-biasing of the gates under gain compression, it is
preferrable to minimize as much as possible the source resistance of the Vg power supply.
Ref. : DSCHA30920356 21-Dec.-00
5/7
Specifications subject to change without notice
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