U M C
The Interrupt Flag Register
and Interrupt Enable
25 and 26,
or
selected bits in this register to facilitate
Register
tively.
are depicted in
controlling individual interrupts without affecting others.
This is accomplished by writing
address 1110
on the
address).
bus
If bit 7 of the data
data
The
may be read directly by the processor. In
bits may be cleared by writing a
this write Operation is a “O”,
“1 in bits 6
tion, individual
into the appropriate bit of the
through 0 clears the corresponding bit in the Interrupt
Enable Register. For “zero” in bits 6 through 0, the
corresponding bit unaffected.
When the proper
are applied to the the
select and register
contents of this register are
on the data bus. Bit 7
of the IRQ output.
This bit
indicates the
to the logic
Setting selected bits in the Interrupt Enable Register is
accomplished by writing to the same address with bit 7 in
=
x
x
+
+
x
x
+
+
x
+
x
the data word set to a logic “1”. In this
“1” in
x
+
IFRO
Note:
X
l o g i c
bits 6 through 0 will set the corresponding bit. For
AND, +=
OR.
bit 7 is not a flag. Therefore, this bit is not
logic “1” into it, lt
be cleared by Clearing all the flags in the register or by
“Zero”, the corresponding bit will be unaffected. The
individual control of the setting and operations
The
very convenient control of the interrupts
Operation.
directly cleared by writing
a
all the
interrupts as
in the next
In addition to setting and Clearing IER bits, the processor
read the contents of this register by placing the proper
address on the register select and
select inputs with the
For
interrupt flag in IFR, there is
a
corresponding
processor
high. Bit 7 will be read as a logic “1
bit in the Interrupt Enable Register. The
Reg 13
Interrupt Flag Register
Reg 14
Interrupt Enable Register
SET BY
CLEAAEO BY
CA1
1. IF BIT7
.
THE
CONTROL IN THE PCR
SELECTED AS
CORRESPONDING
2. IF BIT IS
INTERRUPT.
EACH
INTERRUPT INPUT, THEN READING OR
7
A
IN
DONE, BIT
ENABLESTHE
WRITING THE OUTPUT REGISTER
WILL NOT
THE BIT MUST BE
AS
COARESPONDING INTERRUPT.
3. IF READ OF THIS REGISTER
C L E A A T H E F L A G B I T .
C L E A A E D B Y W R I T I N G I N T O T H E
A
7 WILL BE “1”
AND ALL OTHER BITS WILL REFLECT
DISABLE STATE.
Figure 25. Interrupt Flag Register
Figure 26. Interrupt Enable Register
Ordering Information
Part Number
Frequency
UM6522
1 MHz
40L DIP
40L DIP
2 MHz
5 - 3 4
UMC [ UMC CORPORATION ]
