and the peripheral device must
Ready”
with the “Data Taken” This be accomplished
the interrupt flag and Clearing the “Data Ready” output.
This sequence shown in Figure 13.
on both the PA port and the PB port on the
CA2 or CB2 act as a “Data Ready” output in either the
handshake mode or pulse mode and CA1 or CB1
of
modes for
CA2, CB1 , and CB2
is accomplished by the Peripheral Control Register (Figure
the “Data Taken”
from the peripheral device, setting
DATA READY
OUTPUT
OPERATION
“DATA TAKEN”
HANDSHAKE MODE
“DATA TAKEN”
PULSE MODE
Figure 12. Read Handshake Timing (Port A,
ORA. ORB
OPERATION
“ D A T A R E A D Y ”
HANDSHAKE MODE
CB21
“DATA READY”
PULSE MODE
“DATA TAKEN”
OUTPUT
Figure 13. Write Handshake Timing
PERIPHERAL CONTROL REGISTER
REG 12
CONTROL
CA1 INTERRUPT CONTROL
0
1
NEGATIVE ACTIVE
POSITIVE ACTIVE EDGE
7
0
0
OPERATION
ACTIVE EDGE
0
I N O E P E N D E N T I N T E R R U P T
INPUT
CA2 CONTROL
0
0
1
0
INPUT POSITIVE ACTIVE EDGE
1
1
INDEPENDENT INTERRUPT
INPUT POS EDGE
1
1
1
0
0
1
0
1
HANDSHAKE OUTPUT
PULSE OUTPUT
LOW OUTPUT
HIGH OUTPUT
0
1
1
I
N
T
E
R
R
U
P
T
C
O
N
T
R
O
L
-
0
=
NEGATIVE ACTIVE EDGE
1
= POSITIVE ACTIVE EDGE
NOTE ACCOMPANYING FIGURE 251
Figure 14.
CB2 Control
Timer Operation
Timer, Tl, consists of two X-Bit latches and a
decrement at the clock rate. Upon reaching “zero”, an
if the interrupt is enabled. The timer will then disable any
interrupts, or (when programmed
will
atically transfer the contents of the latches into the
and begin to decrement again. In addition, the timer
interrupt flag will be set, and
will go low if the
clock rate. Upon reaching
will be set, and will go low
rupt decrements at the
be programmed to invert the output
on a peripheral
an interrupt
5 - 2 7
UMC [ UMC CORPORATION ]
