pin
time it “firnes-out.”
of these modes is
Two bits are provided in the Auxiliary Control Register
6 and to of the Tl operating modes.
discussed
The four possible modes are depicted in Figure 17.
The Tl counter
Figure 16
depicted in Figure 15 and the
in
Reg 4 Timer 1 Low-Order Counter
Reg 5 Timer 1 High-Order Counter
COUNT VALUE
WRITE -6 BITS LOADED INTO
LATCHES. ALSO,
-8 BITS ARE
C O N T E N T S A R E T R A N S F E R R E D I N T O L O W
O R D E R C O U N T E R A T T H E T H E H I G H O R D E R
INTO Tl LOW-ORDER LATCHES.
AT
TIME BOTH HIGH AND LOW-ORDER LATCHES
A R E T R A N S F E R R E D I N T O T H E T l C O U N T E R . A N D
INITIATES COUNTDOWN
RESET
Tl INTERRUPT FLAG
ALSO
C
O U N T E R
BITS FROM Tl LOW-ORDER COUNTER
FERRED TO MPU. IN ADDITION. Tl INTERRUPT FLAG
RESET (BIT IN INTERRUPT FLAG REGISTER).
TRANS-
READ
BITS FROM Tl HIGH-ORDER COUNTER TRANSFERRED
TO MPU.
6
Figure 15. Tl Counter Registers
Reg 7 Timer 1 High-Order Latches
Reg 6 Timer 1 Low-Order Latches
1
2
4
1
COUNT VALUE
COUNT VALLJE
16
BITS ARE LOADED INTO Tl LOW-ORDER LATCHES
T H I S O P E R A T I O N N O D I F F E R E N T
BITS LOADED INTO Tl HIGH-ORDER LATCHES. UNLIKE
REG. OPERATION. NO LATCH-TO-COUNTER TRANS
A
4
WRITE INTO REG
4
FERS TAKE PLACE.
R E A D -
FAOM Tl
LATCHES TRANSFERRED
READ-
BITS FROM Tl HIGH-ORDER LATCHES ARE TRANS-
FERRED TO MPU
T O
UNLIKE AEG
CAUSE RESET OF Tl INTERRUPT
4
OPERATION,
LAG.
DOES NCT
Figure 16.
Registers
Reg 11 Auxiliary Control Register
Figure 17. Auxiliary Control Register
Note. The
the
does not
directly to the
order counter
counter
this half of the counter is loaded
it may not be to write to the low
counter.
from
counter in
In
when the processor writes to the high
some applications
the timing Operation is
by writing to the high
5 - 2 8
UMC [ UMC CORPORATION ]
