Associated with
bit. This be set or cleared by the processor to enable
interrupting the processor from the corresponding interrupt
interrupt flag is an interrupt enable
processor.
In the
all the interrupt flags are
in
flag.
an interrupt flag is set to a logic “1” byan interrupt-
one register. In addition, bit 7 of this register will be read
as a logic when an interrupt exists within the This
very convenient polling of several devices within
to the of an interrupt.
ing
is set to a
low.
and the corresponding interrupt enable bit
the Interrupt Request Output
is an output
to other devices in the
will go
b e
to interrupt the
a
WRITE
OPERATION
PE6 INPUT
OUTPUT
N-l
Figure 21. Timer 2 Pulse Counting
Reg 10 Shift Register
Reg
H
Reg 11
Auxiliary Cuntrol Register
SHIFT REGISTER MODE CONTROL
SHIFT REGISTER BITS
1. WHEN SHIFTING OUT. BIT
OUT AND SIMULTANEOUSLY
7
THE FIRST
ROTATED BACK
BIT
0 AND SHIFTED TOWARDS BIT 7.
SHIFT OUT
C
2. WHEN SHIFTING IN. BITS INITIALLY ENTER
BIT AND ARE SHIFTED TOWARDS BIT 7.
0
Figure 22. SR and ACR Control Bits
SR Disabled
The 000 mode is used to disable the Shift Register. In this
mode the microprocessor read the SR, but the
shifting operating is disabled and Operation of CB1 and CB2
is by the appropriate bits in the Peripheral
.
T2
The shifting Operation is triggered by writing
reading
the shift register. Data is shifted first into the low
bit of SR and is then shifted into the next
bit of the shift register on the negative-going edge of
Control Register
Flag is disabled
In this mode the SR Interrupt
to a logic
pulse. The input data should
positive-going edge of the CB1
shifted into the shift register
before the
pulse. This data is
Shift in
In the 001 mode the shifting rate is
8 bits of Shift
Cuntrol of T2
the
of the CB1
cycle
pulse.
by the low
following the positive-going
are generated on the
After 8 CB1
the shift register interrupt flag
will go low.
CB1 Pin to control shifting in external devices. The time
between transitions of this output is a of
the period and the contents of the low
will be set and
WRITE OR READ
SHIFT REG.
CB1 OUTPUT
SHIFT CLOCK
CB2 INPUT
DATA
UMC [ UMC CORPORATION ]
