U M C
Shift in
In mode 010 the shift rate is a
clock frequency. CB1 becomes an output which generates
shift for controlling external devices. Timer
erates as an independent interval timer and has no
Control of
of the
writing the Shift Register. Data is shifted first into bit
0 and is then shifted into the next
shift register on the trailing edge of
bit of the
2
clock pulse.
After 8 clock
the shift register interrupt flag will
on CB1 will stop.
on SR. The shifting Operation is
by reading or
be set, and the output clock
SR
OPERATION
OUTPUT
SHIFT CLOCK
CB2 INPUT
DATA
Figure 23-2 Shift Register Input Modes
Shift in
Control of Externat
Shift Register resets the Interrupt flag and
SR counter to count another 8
the
In mode Oll CB1 becomes an input. This
an
ternal
to load the shift register at its own
The shift register counter will interrupt the
Note that the data is shifted
the first
clock
cycle following the positive-going edge of the CB1 shift
pulse. For this reason, data must be held stable
the first full cycle after CB1 goes high.
time 8 bits have been shifted in. However, the shift
register counter does not stop the shifting Operation;
it
as a pulse counter. Reading
writing the
CB1 OUTPUT
SHIFT CLOCK
Figure 23-3 Shift Register Input Modes
Shift Out Free-Running at T2 Rate
into the shift register will be clocked onto CR2 repeatedly.
Mode
is very similar to mode 101 in which the shift
In this mode the shift register counter is disabled, and
is never
rate is set by T2. However, in mode 100 the SR Counter
does not stop the shift Operation.
Shift Register
bit 7
is circulated back into bit 0, the 8 bits loaded
SR
OPERATION
CB1 OUTPUT
SHIFT CLOCK
CB2 INPUT
DATA
Figure 24-1 Shift Register Output Modes
5 - 3 2
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