Tripath Technology, Inc. – Preliminary Technical Information
When DCX is set to ‘1’, automatic DC calibration is disabled. The default value of DCX is set by the
BYP_CAL input. When BYP_CAL = 5V, DCX will be ‘1’ at power-on. When BYP_CAL = GND, DCX will be
‘0’ at power-on. DCX works in conjunction with the CAB bit. DCX should be set to the same value as CAB.
DCB controls the method of automatic DC calibration that will be used. DCB should be set to ‘1’ if a bridged
output stage is being used. DCB should be cleared to ‘0’ if a single ended output stage is being used. The
BCn bits work in conjunction with the DCB bit. When DCB is set to '1', the BCn bits that correspond to the
channels that have bridged output stages connected to them should be set to '1'. When DCB is cleared to
'0', all of the BCn bits should be cleared to '0'. The default value of DCB will be the inversion of the
SE/BRGB pin. When SE/BRGB = GND, DCB will be '1' at power-on. When SE/BRGB = 5V, DCB will be '0'
at power-on.
The DEL control bit enables the on-chip delay compensation. Delay compensation corrects for loop
instability that can be caused by propagation delay through power stages. It should always be set to ‘1’.
Individual Hard Mute Control
Addr
77h
Register Name
Individual Hard Mute Control
Default
D7
0
D6
HM4
0
D5
HM3
0
D4
HM2
0
D3
HM1
0
D2
0
D1
0
D0
0
0
0
0
0
Setting an HMn bit to ‘1’ stops switching on an individual output channel. Clearing the bit to ‘0’ resumes
normal operation.
Post-Gain Control
Addr
7Ah
Register Name
Post Gain Control
Default
D7
GN41
ext
D6
GN40
ext
D5
GN31
ext
D4
GN30
ext
D3
GN21
ext
D2
GN20
ext
D1
GN11
ext
D0
GN10
ext
Post-gain adjusts the maximum output level with respect to the power stage supply voltage. Post gain
settings ‘00’ and ‘01’ decrease the noise floor while limiting output power. Post gain setting ‘11’ allows a
signal to be severely clipped for maximum power measurements.
GNn<1:0>
Post-gain
00
01
10
11
-6.5 dB
-3.5 dB
0 dB
+2.5 dB
OV and SLEEPB control
Addr
7Ch
Register Name
OV and SLEEPB Control
Default
D7
0
D6
0
D5
D4
D3
0
D2
0
D1
0
D0
0
SLPB
1
OVDB
1
0
0
0
0
0
0
Clearing the OVDB control bit to ‘0’ disables the over voltage sense circuit. Setting the OVDB control bit to
‘1’ returns the over voltage sense circuit to normal operation. The under voltage sense circuit functions
normally regardless of the state of OVDB.
The SLPB control bit determines the state of the SLEEPB_OUT pin. When SLPB is set to '0', SLEEP_OUT
is 0V. When SLPB is set to '1', SLEEP_OUT is 5V. This pin can be used to put the power stage IC into sleep
mode. The SLPB control bit has no internal affect on the TCD6001. If the power stage does not have a
SLEEPB input, the SLEEPB_OUT output can be used as a general purpose logic output.
33
TCD6001 – JL/Rev. 0.9/07.05
TRIPATH [ TRIPATH TECHNOLOGY INC. ]
