Tripath Technology, Inc. – Preliminary Technical Information
Processor Y-output delay
YD<3:0>
Actual count
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
15 nS
30 nS
3
45 nS
4
60 nS
5
75 nS
6
90 nS
7
105 nS
120 nS
135 nS
150 nS
165 nS
180 nS
195 nS
210 nS
225 nS
240 nS
8
9
10
11
12
13
14
15
16
Truth table for Y-output delay control.
Startup Burst Control
Addr
73h
Register Name
Startup Burst Control
Default
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
STB1
0
D0
STB0
0
0
0
0
0
0
0
The STBn control bits enable startup bursts for driving bootstrapped output stages such as the TP2150B
and TP2350. When using power stages that do not require startup bursts, STB1 and STB0 should be
cleared to 0 to minimize turn-on pops.
STB<1:0>
Number of startup pulses
00
01
10
11
0
4
8
16
.
Headphone and Logic Output Control
Addr
74h
Register Name
Headphone and Logic Output
Default
D7
0
D6
YSN
0
D5
HPO
0
D4
TO
0
D3
0
D2
0
D1
0
D0
0
0
0
0
0
0
Setting the TO control bit to ‘1’ forces the TST_EN output pin to go high. This pin can be used to put the
power stage IC into test mode. If the power stage does not have a TST_EN input, the TST_EN output can
be used as a general purpose logic output.
Setting HPO to ‘1’ immediately stops all switching without muting the headphone amplifier outputs. This
function can be used to mute all power stage outputs while the user listens to the headphone output. If any
of the power stages being used only have single Yn inputs (like the TPD2075 and TPD2125) instead of Y/Yb
combinations, HMF should be used instead. HPO should be cleared to '0' for normal operation.
31
TCD6001 – JL/Rev. 0.9/07.05
TRIPATH [ TRIPATH TECHNOLOGY INC. ]
