Tripath Technology, Inc. – Preliminary Technical Information
Dither Control
Addr
39h
Register Name
Dither Control
Default
D7
DT7
0
D6
DT6
0
D5
DT5
0
D4
DT4
0
D3
DT3
0
D2
DT2
0
D1
DT1
0
D0
DT0
0
This register is used to set the amount of dither in the system. It should be set to 3Ch for normal operation.
Fault Latch Control
Addr
3Ah
Register Name
Fault Latch Control
Default
D7
0
D6
0
D5
0
D4
0
D3
0
D2
FLD
1
D1
FLC
0
D0
0
0
0
0
0
0
0
FLD and FLC control the TCD6001 behavior after FAULT has been asserted.
If FLD is set to ‘1’, the TCD6001 will automatically un-mute after FAULT is released (floated).
If FLD is cleared to ‘0’, the TCD6001 will remain latched in this FAULT-based muted condition until the
FAULT pin is released and FLC undergoes a ‘0’ to ‘1’ transition.
Saturation Clamp
Addr
3Bh
3Ch
Register Name
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Saturation Clamp LSB
Saturation Clamp MSB
1
1
1
0
0
1
1
1
The Saturation Clamp is a 16 bit word that determines the internal digital saturation point. It should be set to
E7FFh for the maximum range of operation.
Predictive Gain Control
Addr
3Dh
Register Name
Predictive Gain Control
Default
D7
PGC
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
0
0
0
0
0
0
0
Predictive Gain Control is enabled when PGC is set to ‘1’. It is disabled when PGC is cleared to ‘0’. PGC
should not be turned on or off while not in hard-mute. Doing so will have unpredictable results.
Output Delay Control
Addr
71h
72h
Register Name
Output Delay Control
Output Delay Control
Default
D7
YD23
YD43
0
D6
YD22
YD42
0
D5
YD21
YD41
0
D4
YD20
YD40
0
D3
YD13
YD33
0
D2
YD12
YD32
0
D1
YD11
YD31
0
D0
YD10
YD30
0
The loop delay of each channel can be selectively increased by programming its corresponding 4-bit field.
Adjusting loop delay can be used to control power stage switching frequency. Switching frequencies should
be staggered by at least 40kHz to avoid beat frequencies that can increase the noise floor.
30
TCD6001 – JL/Rev. 0.9/07.05
TRIPATH [ TRIPATH TECHNOLOGY INC. ]
