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TMC8462-BA 参数 Datasheet PDF下载

TMC8462-BA图片预览
型号: TMC8462-BA
PDF下载: 下载PDF文件 查看货源
内容描述: [Dual Integrated 100-Mbit Ethernet PHY]
分类和应用:
文件页数/大小: 204 页 / 12251 K
品牌: TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
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TMC8462 Datasheet Document Revision V1.4 2018-May -09  
93 / 204  
6.4.15 Distributed Clocks Receive Times  
Depending on the available width of the Distributed Clocks feature the time stamp registers are either 32  
bit (4 bytes) or 64 bits (8 bytes) wide. Please check the feature summary of the respective TRINAMIC ESC  
device.  
6.4.15.1 Receive Time Port 0 (0x0900:0x0903)  
Bit  
Description  
ECAT  
PDI  
Reset Value  
31:0  
Write:  
r/w  
r/-  
A write access to register 0x0900 with BWR or (special  
FPWR latches the local time of the beginning of func-  
the receive frame (start rst bit of preamble) at tion)  
each port.  
Read:  
Local time of the beginning of the last receive  
frame containing a write access to this register.  
Table 88: Register 0x0900:0x0903 (Rcv Time P0)  
Note  
The time stamps cannot be read in the same frame in which this register was  
written.  
6.4.15.2 Receive Time Port 1 (0x0904:0x0907)  
Bit  
Description  
ECAT  
PDI  
Reset Value  
31:0  
Local time of the beginning of a frame (start r/-  
rst bit of preamble) received at port 1 contain-  
ing a BWR or FPWR to Register 0x0900.  
r/-  
Table 89: Register 0x0904:0x0907 (Rcv Time P1)  
©2018 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany  
Terms of delivery and rights to technical change reserved.  
Download newest version at www.trinamic.com  
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