TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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6.4.14.3 Control Register (+0x4)
Bit
Description
ECAT
PDI
Reset Value
1:0
Operation Mode:
r/(w)
r/-
00: Buffered (3 buffer mode)
01: Reserved
10: Mailbox (Single buffer mode)
11: Reserved
3:2
Direction:
r/(w)
r/-
00: Read: ECAT read access, PDI write access.
01: Write: ECAT write access, PDI read access.
10: Reserved
11: Reserved
4
5
6
7
Interrupt in ECAT Event Request Register:
0: Disabled
1: Enabled
r/(w)
r/(w)
r/w
r/-
r/-
r/-
r/-
Interrupt in PDI Event Request Register:
0: Disabled
1: Enabled
Watchdog Trigger Enable:
0: Disabled
1: Enabled
Reserved, write 0
r/-
Table 84: Register 0x0804+y*8 (SM Control)
Note
r/(w): Register can only be written if SyncManager is disabled (+0x6.0 = 0).
6.4.14.4 Status Register (+0x5)
Bit
Description
ECAT
PDI
Reset Value
0
Interrupt Write:
r/-
r/-
1: Interrupt after buffer was completely and
successfully written
0: Interrupt cleared after first byte of buffer
was read
NOTE: This interrupt is signaled to the reading
side if enabled in the SM Control register.
1
Interrupt Read:
r/-
r/-
1: Interrupt after buffer was completely and
successful read
0: Interrupt cleared after first byte of buffer
was written
NOTE: This interrupt is signaled to the writing
side if enabled in the SM Control register.
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