TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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6.4.16.6 Speed Counter Start (0x0930:0x0931)
Bit
Description
ECAT
PDI
Reset Value
14:0
Bandwidth for adjustment of local copy of Sys- r/(w)
r/(w)
tem Time (larger values smaller bandwidth
→
and smoother adjustment)
A write access resets System Time Differ-
ence (0x092C:0x092F) and Speed Counter Diff
(
0x0932:0x0933). Minimum value: 0x0080 to
0x3FFF
15
Reserved, write 0
r/(w)
r/-
Table 95: Register 0x0930:0x931 (Speed Cnt Start)
Note
Write access to this register depends upon ESC configuration (typically ECAT, PDI
only with explicit ESC configuration: System Time PDI controlled).
6.4.16.7 Speed Counter Diff (0x0932:0x0933)
Bit
Description
ECAT
PDI
Reset Value
15:0
Representation of the deviation between local r/-
clock period and reference clock’s clock period
(representation: two’s complement) Range:
±(Speed Counter Start - 0x7F)
r/-
Table 96: Register 0x0932:0x0933 (Speed Cnt Diff)
Note
Calculate the clock deviation after System Time Difference has settled at a low
value as follows:
SpeedCntDiff
Deviation
=
5∗(SpeedCntStart+SpeedCntDiff+2)∗(SpeedCntStart−SpeedCntDiff+2)
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