TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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5.3 Ethernet Physical Layer Connection
TMC8462 comes with two integrated 100-Mbit Ethernet PHYs eliminating the need for external PHY
components. The physical media interface can connect to (shielded) twisted pair copper buses ((S)TPC).
Port signals with index 0 represent the EtherCAT IN port. Port signals with index 1 represent the EtherCAT
OUT port.
Figure 17: Physical bus interface pins
TMC8462 pin
TNx
Description
Negative pin of differential transmit output pair
Positive pin of differential transmit output pair
Negative pin of differential receive output pair
Positive pin of differential receive output pair
TPx
RNx
RPx
REGOUTx
This is a regulator power output. A 10uF and 0.1uF should be connected to
this pin for filtering power noise.
MCLK
PHY configuration clock output
PHY configuration data in-/output
MDIO
Table 6: Physical bus interface pin description
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