TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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5.2 MFC IO Control Interface
The MFC IO block of the TMC8462 comes with a dedicated SPI slave interface to allow direct access from
a local application controller. It is called MFC CTRL SPI interface. This interface to the MFC IO block’s
functions is always available, even if the EtherCAT state machine is currently not in operational state (OP).
Protocol structure and timing are identical to the PDI SPI.
The MFC Control SPI is a SPI mode 3 slave with low active chip select. The SPI clock frequency can be up to
30MHz. The following diagram shows all signals related to the MFC CTRL SPI interface.
Figure 12: MFC control signals
TMC8462 pin
Description
Typical pin on a MCU
MFC_CTRL_SPI_CSN
MFC_CTRL_SPI_SCK
MFC_CTRL_SPI_MOSI
MFC_CTRL_SPI_MISO
MFC_IRQ
SPI chip select for the TMC8462 PDI
SPI master clock
SSx
SCK
Master out slave in data
Master in slave out data
Configurable IRQ from MFC IO block
MOSI
MISO
General purpose Input
PDI_SHARED_BUS
0: separate SPI buses for PDI and MFC CTRL; 1:
shared/common SPI bus for PDI and MFC CTRL
General purpose Output
or connected to either
with 2 CSN signals using the PDI SPI bus. The SPI ground or 3.3V.
bus signals MFC_CTRL_SPI_SCK,
MFC_CTRL_SPI_MISO, MFC_CTRL_SPI_MOSI can
be left open in this case
Table 5: MFC CTRL SPI signal description
5.2.1 SPI Protocol description
The protocol of the MFC CTRL SPI is the same as the PDI SPI interface (see section 5.1.1) The addresses for
register access are calculated using the register number and the byte number in each register. To calculate
the address, the register number is shifted left by 4 bits and the byte number is added as the 4 lowest bits.
Access using the 3 byte addressing mode is possible, and can be used when 2 byte mode is not imple-
mented for the PDI SPI but since the highest bits of the address are always 0, accessing the MFC Control
SPI via 2 byte mode is sufficient.
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