TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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Figure 13: MFC CTRL SPI 2 byte addressing
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Figure 14: MFC CTRL SPI 3 byte addressing
5.2.2 Timing example
This example shows a generic MFC register read access with wait state. The delays between the transferred
bytes are just to show the byte boundaries and are not required.
Figure 15: MFC SPI timing example
5.2.3 Sharing Bus Lines with the PDI SPI
To reduce the number of signals on the PCB or if the local application controller has only one SPI interface,
the MFC CTRL SPI bus can share the SPI bus signals of the PDI SPI, requiring only separate chip select
signals. In this case, both interfaces are internally switched to the PDI SPI interface pins. The original MFC
CTRL SPI signals (MOSI, MISO, and SCK) remain unconnected in this case. Only the MFC_CTRL_SPI_CSN
pin/signal must be used if the MFCIO block is accessed.
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