TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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7.3.1.2 Register 1 – ENC_STATUS
Bit
Description
ECAT
PDI
Range [Unit]
0
n_event
r+c/-
r+c/-
1: Encoder N event detected. Status bit is
cleared on read: Read (R) + clear (C)
This event can also be ORed into the interrupt
output signal. See Register 51 and 52.
7:1
Reserved
r/-
r/-
Table 126: MFC IO Register 1 – ENC_STATUS
7.3.1.3 Register 2 – X_ENC (write)
Bit
Description
ECAT
PDI
Range [Unit]
31:0
Actual encoder position (signed)
r/w
r/w
−231. . . +(231) − 1
Table 127: MFC IO Register 2 – X_ENC (write)
7.3.1.4 Register 3 – X_ENC (read)
Bit
Description
ECAT
PDI
Range [Unit]
31:0
Actual encoder position (signed)
r/-
r/-
−231. . . +(231) − 1
Table 128: MFC IO Register 3 – X_ENC (read)
7.3.1.5 Register 4 – ENC_CONST
Bit
Description
ECAT
PDI
Range [Unit]
31:0
Accumulation constant (signed) 16 bit integer r/w
part, 16 bit fractional part
r/w
binary:
±[µsteps/216]
±(0 . . . 32767.9999847)
X_ENC accumulates
decimal:
ENC_CONST
±
(binary)
±(0 . . . 32767.9999)
16
∗X_ENC)
or(2
reset default =
65536)
1.0(=
ENC_CONST
(104∗X_ENC)
±
(decimal)
ENC_MODE bit enc_sel_decimal switches be-
tween decimal and binary setting. Use the sign,
to match rotation direction!
Table 129: MFC IO Register 4 – ENC_CONST
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