TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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7.3.2 SPI Master Interface
7.3.2.1 Register 6 – SPI_RX_DATA
Bit
Description
ECAT
PDI
Range [Unit]
63:0
Received data from last SPI transfer
For SPI transfers with less than 64 bit, the upper
bits of this register are unused
r/-
r/-
Table 131: MFC IO Register 6 – SPI_RX_DATA
7.3.2.2 Register 7 – SPI_TX_DATA
Bit
Description
ECAT
PDI
Range [Unit]
63:0
Data to transmit on next SPI transfer
For SPI transfers with less than 64 bit, the upper
bits of this register are unused
-/w
-/w
Table 132: MFC IO Register 7 – SPI_TX_DATA
Note
Unless configured otherwise in the SPI_CONF register (bits 10:8), writing data
into this register automatically starts transmission as soon as the highest byte
(according to SPI_LENGTH configuration) has been written.
All bytes to be transmitted must be written to the register within a single access
(via MFC IO Control SPI or from the DPRAM) to ensure data consistency.
7.3.2.3 Register 8 – SPI_CONF
Bit
1:0
2
Description
ECAT
r/w
PDI
r/w
r/w
r/w
Range [Unit]
Selection of SPI slave
reserved
r/w
3
Keep CS low after transfer for transfers greater r/w
than 64bit
4
5
6
7
transmit LSB first
SPI clock phase
SPI clock polarity
reserved
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
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