TMC5130A DATASHEET (Rev. 1.14 / 2017-MAY-15)
40
6.4 Encoder Registers
ENCODER REGISTER SET (0X38…0X3C)
R/W
Addr
n
Register
Description / bit names
Range [Unit]
Encoder configuration and use of N channel
See separate table!
Actual encoder position (signed)
RW
0x38
11 ENCMODE
32 X_ENC
-2^31…
+(2^31)-1
binary:
± [µsteps/2^16]
±(0 …
RW
W
0x39
0x3A
Accumulation constant (signed)
16 bit integer part, 16 bit fractional part
X_ENC accumulates
+/- ENC_CONST / (2^16*X_ENC) (binary)
or
32767.999847)
decimal:
32 ENC_CONST
±(0.0 …
32767.9999)
+/-ENC_CONST / (10^4*X_ENC) (decimal)
reset default =
ENCMODE bit enc_sel_decimal switches 1.0 (=65536)
between decimal and binary setting.
Use the sign, to match rotation direction!
bit 0: n_event
1: Encoder N event detected. Status bit is
cleared on read: Read (R) + clear (C)
This bit is ORed to the interrupt output
signal.
R+C
R
0x3B
0x3C
1
ENC_STATUS
Encoder position X_ENC latched on N event
32 ENC_LATCH
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