TMC4330A Datasheet | Document Revision 1.01 • 2017-JAN-12
14/166
Read/Write
Selection
Principles and
Process
Read and write selection is controlled by the MSB of the address byte (bit 39 of the
SPI datagram). This bit is 0 for read access and 1 for write access. Consequently, the
bit named W is a WRITE_notREAD control bit.
The active high write bit is the MSB of the address byte.
Consequently, 0x80 must be added to the address for a write access.
The SPI interface always delivers data back to the master, independent of
the Write bit W.
Difference between Read and Write Access
If …
Then …
The data transferred back is the data read from the
address which was transmitted with the previous
datagram.
The previous access was a read access.
The previous access was a write access
The data read back mirrors the previously received write
data.
Figure 12: Difference between Read and Write Access
Conclusion:
Consequently, the difference between a read and a write access is that the read access
does not transfer data to the addressed register but it transfers the address only; and
its 32 data bits are dummies.
NOTE:
Please note that the following read delivers back data read from the address
transmitted in the preceding read cycle. The data is latched immediately after the
read request.
A read access request datagram uses dummy write data.
Read data is transferred back to the master with the subsequent read or write access.
AREAS OF
SPECIAL
CONCERN
!
i
Reading multiple registers can be done in a pipelined fashion. Data that is
delivered is latched immediately after the initiated data transfer.
Use of Dummy
Write Data
Read and Write
Access Examples
For read access to register XACTUAL with the address 0x21, the address byte must
be set to 0x21 in the access preceding the read access.
For write access to register VACTUAL, the address byte must be set to
0x80 + 0x22 = 0xA2. For read access, the data bit can have any value, e.g., 0.
Read and Write Access Examples
Action
Data sent to TMC
Data received from TMC
read XACTUAL
read XACTUAL
0x2100000000
0x2100000000
0xSS1) & unused data
0xSS & XACTUAL
write VACTUAL:=
0x00ABCDEF
write VACTUAL:=
0x00123456
0xA200ABCDEF
0xA200123456
0xSS & XACTUAL
0xSS00ABCDEF
Table 4: Read and Write Access Examples
SS is a placeholder for the status bits SPI_STATUS.
1)
© 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights
to technical change reserved. Download newest version at: www.trinamic.com .
Read entire documentation; especially the “Supplemental Directives” on page 160.
MAIN MANUAL
TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
