TMC4330A Datasheet | Document Revision 1.01 • 2017-JAN-12
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SPI Timing Description
The SPI interface is synchronized to the internal system clock, which limits SPI bus clock SCKIN
to a quarter of the system clock frequency. The signal processing of SPI inputs is supported
with internal Schmitt Trigger, but not with RC elements.
NOTE:
In order to avoid glitches at the inputs of the SPI interface between µC and TMC4330A, external RC
elements have to be provided.
Figure 14 shows the timing parameters of an SPI bus transaction, and the table below specifies the parameter
values.
SPI Interface Timing
SPI Interface Timing
Parameter
AC Characteristics:
Symbol Conditions
External clock period: tCLK
Min
Type
Max
Unit
SCKIN valid before or after
change of NSCSIN
tCC
10
ns
Min. time is for
synchronous CLK with
NSCSIN high time
tCSH
tCLK
>2·tCLK+10
ns
SCKIN high one tCH
before SCSIN high only.
Min. time is for
synchronous CLK only.
Min. time is for
SCKIN low time
SCKIN high time
tCL
tCLK
tCLK
>tCLK+10
>tCLK+10
ns
ns
tCH
synchronous CLK only.
SCKIN frequency using
external clock
Assumes synchronous
CLK.
fCLK / 4
(4)
fSCK
MHz
(Example: fCLK = 16 MHz)
SDIIN setup time before
rising edge of SCKIN
SDIIN hold time after rising
edge of SCKIN
tDU
tDH
tDO
10
10
ns
ns
Data out valid time after
falling SCKIN clock edge
No capacitive load on
SDOIN.
tFILT+5 ns
Table 5: SPI Interface Timing
i
tCLK = 1 / fCLK
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