TMC4330A Datasheet | Document Revision 1.01 • 2017-JAN-12
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System Overview
VDD1V8(2x)
POR
CLK_EXT
GND(4x)
VDD5(3x)
NRST
I
I
Host CPU
SPI Interface
R
E
S
E
T
I
I
O
O
NSCSIN
TARGET_REACHED
INTR
Status Flags /
Events
for
Interrupt
Control
SCKIN
SDIIN
SDOIN
SPI
Register Block
I
Motion
Profile
ClkGating
CLK_INT
O
Target
Register(s)
ShadowReg
I
Scan Test
TEST_MODE
Parameters
from/for all
Units
Start / Stop /
Reference Switches
Timer Unit
IO
START
GearRatio
Step/Dir Input
STP_IN
I
I
I
I
I
STOPL
HOME_REF
STOPR
DDS
DIR_IN
Reference
processing
Ramp-Generator
PulseGen
v
Step/Dir Outputor
PWM Output
S-Ramps with 4 Bows
Trapezoid Ramps
Rectangle Ramps
O
O
PID
STPOUT
PWMA
(Sine)
Circles
Internal
Step
DIROUT
PWMB
PID_E
(Cosine)
Encoder (differential)
Pos
Counter
External
Pos
Internal
Pos
Compare
SPI or SSI
ABN
External
PosCounter
or
Commutation
angle
FS
SSI
IO
IO
I
SCLK
SCLK
A
ClosedLoop Unit
Actual
Co-/Sine values
Internal
(Co)Sine LUT
NSCS
NSCLK ANEG
Decoder Unit
SPI
SDI
SDI
B
PWM
Unit
IO
I
SDO
NSDI
BNEG
ABN
N
I
NNEG
Figure 7: System Overview
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