TMC4330A Datasheet | Document Revision 1.01 • 2017-JAN-12
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Input Sample
Rate (SR)
Input sample rate = fCLK 1/2SR where:
SR (extended with a particular name extension) is in [0… 7].
i
This means that the next input value is considered after 2SR clock cycles.
Sample Rate
Configuration
Sample Rate Configuration
Sample Rate
SR Value
0
1
2
3
4
5
6
7
fCLK
fCLK/2
fCLK/4
fCLK/8
fCLK/16
fCLK/32
fCLK/64
fCLK/128
Table 8: Sample Rate Configuration
Digital Filter
Length (FILT_L)
i
i
The filter length FILT_L can be set within the range [0… 7].
The filter length FILT_L specifies the number of sampled bits that must have the
same voltage level to set a new input bit voltage level.
Configuration of Digital Filter Length
Digital Filter
Length
Configuration
Table
Filter Length
FILT_L value
0
1
2
3
4
5
6
7
No filtering.
2 equal bits.
3 equal bits.
4 equal bits.
5 equal bits.
6 equal bits.
7 equal bits.
8 equal bits.
Table 9: Configuration of Digital Filter Length
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