UCD9090
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SLVSA30A –APRIL 2011–REVISED AUGUST 2011
A shutdown on one or more of the master rails can initiate shutdowns of the slave devices. The master
shutdowns can be initiated intentionally or by a fault condition. This method works to coordinate multiple
controllers, but it does not enforce interdependency between rails within a single controller.
The PMBus specification implies that the power-good signal is active when ALL the rails in a controller are
regulating at their programmed voltage. The UCD9090 allows GPIOs to be configured to respond to a desired
subset of power-good signals.
PWM Outputs
FPWM1-8
Pins 10-17 can be configured as fast pulse-width modulators (FPWMs). The frequency range is 15.260 kHz to
125 MHz. FPWMs can be configured as closed-loop margining outputs, fan controllers or general-purpose
PWMs.
Any FPWM pin not used as a PWM output can be configured as a GPIO. One FPWM in a pair can be used as a
PWM output and the other pin can be used as a GPO. The FPWM pins are actively driven low from reset when
used as GPOs.
The frequency settings for the FPWMs apply to pairs of pins:
•
•
•
•
FPWM1 and FPWM2 – same frequency
FPWM3 and FPWM4 – same frequency
FPWM5 and FPWM6 – same frequency
FPWM7 and FPWM8 – same frequency
If an FPWM pin from a pair is not used while its companion is set up to function as a PWM, it is recommended to
configure the unused FPWM pin as an active-low open-drain GPO so that it does not disturb the rest of the
system. By setting an FPWM, it automatically enables the other FPWM within the pair if it was not configured for
any other functionality.
The frequency for the FPWM is derived by dividing down a 250MHz clock. To determine the actual frequency to
which an FPWM can be set, must divide 250MHz by any integer between 2 and (214-1).
The FPWM duty cycle resolution is dependent on the frequency set for a given FPWM. Once the frequency is
known the duty cycle resolution can be calculated as Equation 1.
Change per Step (%)FPWM = frequency ÷ (250 × 106 × 16) × 100
(1)
Take for an example determining the actual frequency and the duty cycle resolution for a 75MHz target
frequency.
1. Divide 250MHz by 75MHz to obtain 3.33.
2. Round off 3.33 to obtain an integer of 3.
3. Divide 250MHz by 3 to obtain actual closest frequency of 83.333MHz.
4. Use Equation 1 to determine duty cycle resolution to obtain 2.0833% duty cycle resolution.
PWM1-2
Pins 22 and 23 can be used as GPIs or PWM outputs. These PWM outputs have an output frequency of 0.93 Hz
to 7.8125 MHz.
The frequency for PWM1 and PWM2 is derived by dividing down a 15.625MHz clock. To determine the actual
frequency to which these PWMs can be set, must divide 15.625MHz by any integer between 2 and (224-1). The
duty cycle resolution will be dependent on the set frequency for PWM1 and PWM2.
The PWM1 or PWM2 duty cycle resolution is dependent on the frequency set for the given PWM. Once the
frequency is known the duty cycle resolution can be calculated as Equation 2
Change per Step (%)PWM1/2 = frequency ÷ 15.625 × 106 × 100
(2)
To determine the closest frequency to 1MHz that PWM1 can be set to calculate as the following:
1. Divide 15.625MHz by 1MHz to obtain 15.625.
2. Round off 15.625 to obtain an integer of 16.
Copyright © 2011, Texas Instruments Incorporated
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