UCD90320
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ZHCSFI3B –AUGUST 2016–REVISED MAY 2019
Figure 29. Example Fault Pins Configuration Window (Global Configuration ►Fault Pins Config)
These listed page-related faults have impact on the fault pin output. SYSTEM_WATCHDOG_TIMEOUT and
RESEQUENCE_ERROR are optional to have impact on the fault pins.
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•
•
•
•
•
•
•
IOUT_OC_FAULT
IOUT_UC_FAULT
OT_FAULT
SEQ_OFF_TIMEOUT
SEQ_ON_TIMEOUT
TON_MAX_FAULT
VOUT_OV_FAULT
VOUT_UV_FAULT
A SYNC_CLK pin is used as a single-wire time synchronization method. A master chip constantly drives a 5-kHz
clock to the slave devices. This function offers a precise time base for multiple UCD90320 devices to respond to
the same fault event at the same time. The configuration window is shown in Figure 30. If the system uses only
one UCD90320 device, it is recommended to configure this pin as master clock output. The SYNC_CLK output
can be used as a time base for other purposes if needed.
Figure 30. SYNC_CLK Pin Configuration (Global Configuration ► Misc Config)
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