UCD7100
SLUS651C –MARCH 2005–REVISED MAY 2010
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Current Sensing and Protection
A very fast current limit comparator connected to the CS pin is used to protect the power stage by implementing
cycle-by-cycle current limiting.
The current limit threshold is equal to the lesser of the positive inputs at the current limit comparator. The current
limit threshold can be set to any value between 0.25 V and 1.0 V by applying the desired threshold voltage to the
current limit (ILIM) pin. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver
is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the UCD7K device
receives the next rising edge on the IN pin.
When the CS voltage is below ILIM, the driver output will follow the PWM input. The CLF digital output flag can
be monitored by the host controller to determine when a current limit event occurs and to then apply the
appropriate algorithm to obtain the desired current limit profile.
One of the main benefits of this local protection feature is that the UCD7K devices can protect the power stage if
the software code in the digital controller becomes corrupted and hangs up. If the controller’s PWM output stays
high, the local current sense circuit will turn off the driver output when an over-current condition occurs. The
system would likely go into a retry mode because; most DSP and microcontrollers have on-board watchdog,
brown-out, and other supervisory peripherals to restart the device in the event that it is not operating properly.
But these peripherals typically do not react fast enough to save the power stage. The UCD7K’s local current limit
comparator provides the required fast protection for the power stage.
The CS threshold is 25 mV below the ILIM voltage. This way, if the user attempts to command zero current (ILIM
< 25 mV) while the CS pin is at ground, for example at start-up, the CLF flag latches high until the IN pin
receives a pulse. At start-up it is necessary to ensure that the ILIM pin always greater than the CS pin for the
handshaking to work as described below. If for any reason the CS pin comes to within 25 mV of the ILIM pin
during start-up, then the CLF flag is latched high and the digital controller must poll the UCD7K device, by
sending it a narrow IN pulse. If the fault condition is not present the IN pulse resets the CLF signal to low
indicating that the UCD7K device is ready to process power pulses.
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