UCD7100
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SLUS651C –MARCH 2005–REVISED MAY 2010
Handshaking
The UCD7K family of devices have a built-in handshaking feature to facilitate efficient start-up of the digitally
controlled power supply. At start-up the CLF flag is held high until all the internal and external supply voltages of
the UCD7K device are within their operating range. Once the supply voltages are within acceptable limits, the
CLF goes low and the device will process input drive signals. The micro-controller should monitor the CLF flag at
start-up and wait for the CLF flag to go LOW before sending power pulses to the UCD7K device.
Driver Output
The high-current output stage of the UCD7K device family is capable of supplying ±4-A peak current pulses and
swings to both VDD and GND. The driver outputs follows the state of the IN pin provided that the VDD and 3V3
voltages are above their respective under-voltage lockout threshold.
The drive output utilizes Texas Instruments’ TrueDrive™ architecture, which delivers rated current into the gate
of a MOSFET when it is most needed during the Miller plateau region of the switching transition providing
efficiency gains.
TrueDrive™ consists of pullup/ pulldown circuits using bipolar and MOSFET transistors in parallel. The peak
output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is
the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of
the bipolar transistor. This hybrid output stage also allows efficient current sourcing at low supply voltages.
Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the
external MOSFET. This means that in many cases, external-schottky-clamp diodes are not required.
Source/Sink Capabilities During Miller Plateau
Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable
operation. The UCD7K drivers have been optimized to provide maximum drive to a power MOSFET during the
Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between
the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate
capacitance with current supplied or removed by the driver device. See Reference [1]
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