UCD7100
SLUS651C –MARCH 2005–REVISED MAY 2010
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ELECTRICAL CHARACTERISTICS (continued)
VDD = 12 V, 4.7-µF capacitor from VDD to GND, TA = TJ = -40°C to 105°C, (unless otherwise noted).
PARAMETER
CURRENT SENSE COMPARATOR
Bias voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
Includes CS comp offset
5
25
–1
25
25
50
mV
uA
Input bias current
Propagation delay from CS to OUTx ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV
Propagation delay from CS to CLF ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV
CURRENT SENSE DISCHARGE TRANSISTOR
40
50
ns
Discharge resistance
IN = low, resistance from CS to AGND
10
35
75
Ω
OUTPUT DRIVERS
(1)
Source current
VDD = 12 V, IN = high, OUT = 5 V
VDD = 12 V, IN = low, OUT = 5 V
VDD = 4.75 V, IN = high, OUT = 0
VDD = 4.75 V, IN = low, OUT = 4.75 V
CLOAD = 2.2 nF, VDD = 12 V
4
4
(1)
Sink current
A
Source current(1)
2
(1)
Sink current
3
(1)
Rise time, tR
10
10
0.8
20
15
ns
(1)
Fall time, tF
CLOAD = 2.2 nF, VDD = 12 V
Output with VDD < UVLO
VDD = 1.0 V, ISINK = 10 mA
1.2
V
Propagation delay from IN to OUTx,
tD1
CLOAD = 2.2 nF, VDD = 12 V, CLK rising
20
35
ns
(1) Ensured by design. Not 100% tested in production.
VIT+
INPUT
VIT−
t
F
t
F
90%
t
D1
t
D2
OUTPUT
10%
NOTE
The 10% and 90% thresholds depict the dynamics of the bipolar output devices that
dominate the power MOSFET transition through the Miller regions of operation.
4
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