UCC28951
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ZHCSIQ7A –AUGUST 2018 –REVISED DECEMBER 2021
VDROP is the minimum input voltage where the converter can still maintain output regulation (see 方程式92). The
converter’s input voltage would only drop down this low during a brownout or line-drop condition if this
converter was following a PFC pre-regulator.
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ç
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÷
ø
2´DCLAMP ´ VRDSON + a1´(VOUT + VRDSON
)
VDROP
=
= 276.2V
DCLAMP
(92)
CIN was calculated in 方程式93 based on one line cycle of holdup:
1
2´POUT
´
60Hz
CIN ³
» 364mF
2
V
2 - VDROP
(
)
IN
(93)
(94)
Calculate the high-frequency input capacitor RMS current (ICINRMS) using 方程式94.
P
2
OUT
I
=
I
−
= 1.8 A
× η
CINRMS
PRMS1
V
VIN min
To meet the input capacitance and RMS current requirements for this design, a 330-µF capacitor was chosen
from Panasonic part number EETHC2W331EA:
CIN = 330 µF
This capacitor has a high frequency (ESRCIN) of 150 mΩ and is measured with an impedance analyzer at 200
kHz. ESRCIN = 0.150 Ω
Estimate the CIN power dissipation (PCIN) using 方程式95:
2
PCIN = ICINRMS ´ESRCIN = 0.5W
(95)
And recalculate the remaining power budget using 方程式96:
P
= P
-PCIN » 6.0W
BUDGET
BUDGET
(96)
There is approximately 6.0 W that remains in the power budget for the current-sensing network, to bias the
control device, and for all resistors supporting the control device.
8.2.2.10 Current Sense Network (CT, RCS, R7, DA)
The CT chosen for this design has a turns ratio (CTRAT) of 100:1 in 方程式97:
IP
CTRAT
=
= 100
IS
(97)
(98)
Calculate nominal peak current (IP1) at VINMIN
:
The peak primary current is calculated using 方程式98:
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ø
POUT
DILOUT
V
´DMAX
1
INMIN
I =
+
+
» 3.3A
P1
VOUT ´ h
2
a1 LMAG ´ 2´F
SW
The CS pin voltage where peak current limit will trip is:
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Product Folder Links: UCC28951
English Data Sheet: SLUSDB2
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