UCC28951
www.ti.com.cn
ZHCSIQ7A –AUGUST 2018 –REVISED DECEMBER 2021
P
= P
-PCOUT » 25.2W
BUDGET
BUDGET
(74)
8.2.2.8 Select FETs QE and QF
Selecting FETs for a design is an iterative process. To meet the power requirements of this design, we select 75-
V, 120-A FETs, from Fairchild, part number FDP032N08. These FETs have the following characteristics.
QEg = 152nC
(75)
Rds(on)QE = 3.2mW
(76)
Calculate average FET COSS (COSS_QE_AVG) based on the data sheet parameters for COSS (COSS_SPEC), and
drain to source voltage where COSS_SPEC was measured (Vds_spec), and the maximum drain to source voltage in
the design (VdsQE) that will be applied to the FET in the application.
The voltage across FET QE and QF when they are of isf:
2V
INMAX
VdsQE
=
= 39 V
a1
(77)
(78)
(79)
The voltage where FET COSS is specified and tested in the FET data sheet:
Vds _ spec = 25V
The specified output capacitance from FET data sheet is:
COSS _ SPEC = 1810pF
The average QE and QF COSS [2] is calculated using 方程式80:
Vds_SPEC
COSS_QE_ AVG = COSS_SPEC
» 1.9nF
VdsQE
(80)
(81)
The QE and QF RMS current are:
IQE _RMS = ISRMS = 36.0A
To estimate FET switching loss the Vg vs. Qg curve from the FET data sheet needs to be studied. First the gate
charge at the beginning of the miller plateau needs to be determined (QEMILLER_MIN) and the gate charge at the
end of the miller plateau (QEMILLER_MAX) for the given VDS
.
The maximum gate charge at the end of the miller plateau is:
QEMILLER _MAX » 100nC
(82)
(83)
The minimum gate charge at the beginning of the miller plateau is:
QEMILLER _MIN » 52nC
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: UCC28951
English Data Sheet: SLUSDB2